Integrated circuit (IC) memories commonly have manufacturing or fabrication defects due to undesirable variations in materials or processes over the surface of a semiconductor wafer or due to inadvertent damage to the wafer or IC during processing. Such defects result in localized impairment of IC functionality. The impairment is commonly limited to only a few rows or columns out of many thousands on the IC (or memory block of an IC having multiple blocks of memory). Therefore, rather than scrapping the entire IC or some other radical solution, so-called “repair” techniques have been developed to repair the defective rows or columns of memory by substituting a “spare” row or column for each defective row or column.
In accordance with some common repair techniques, the IC includes a group of fuses associated with a memory block. A fuse is a region on the IC die that can be configured or set to a state in which it encodes a binary bit (i.e., “1” or “0”) in a non-volatile manner. Various types of fuses are known. For example, a common type of fuse comprises a metal region that can be reconfigured from a very low impedance to a very high impedance by briefly subjecting it to a relatively high voltage, thereby “blowing” or “burning” the fuse, as the effect is referred to in the art. The fuses can be burned to encode the information needed to repair the defective rows or columns. Each fuse commonly corresponds to exactly one bit of repair information. A number of bits of repair information, such as, for example, ten bits, may be needed to repair a memory block. That is, the repair logic requires this number of bits as an input to be able to properly substitute a spare row or column for a defective row or column in a particular memory block. The bits of repair information commonly provide the repair logic with information at least sufficient to identify a row or column, and may in some instances provide the repair logic with additional information.
Repairing IC memory blocks in a complex application-specific integrated circuit (ASIC) is hampered by the fact that memory blocks are distributed throughout the ASIC as part of numerous core logic blocks. A technique that has been developed to repair ASIC memory blocks involves what is known as a repair chain. A repair chain is a serial or daisy-chained arrangement of flip-flops. In an ASIC having, for example, 2,000 memory blocks, each having repair logic associated with it that requires ten bits of repair information as an input, the repair chain can have 20,000 flip-flops. Accordingly, the IC commonly has 20,000 fuses.
Each core logic block having at least one memory block includes a portion of the repair chain having a number of flip-flops equal to the number of bits of repair information required to repair the memory block. As part of the fabrication process, the defective rows or columns are identified, and the fuses are burned with corresponding repair information. Once burned with repair information in this manner, the ASIC can be included as part of an electronic system as though it had no defects. Each time the IC is powered up as part of the electronic system, repair control logic in the IC reads the repair information (bits) from the fuses and sequentially outputs the bits to the repair chain. That is, as each bit is read, the bit is shifted into, or becomes the next bit of, a serial data stream. Thus, in the foregoing example, 20,000 bits are read from the fuses and serially shifted into the 20,000 flip-flops of the repair chain. The repair logic in each core logic block having at least one memory block uses the bits of repair information stored in the group of flip-flops associated with that core logic block to substitute one or more spare rows or columns for the one or more defective rows or columns identified by those bits. The substitution commonly involves switching some signal paths from the defective row or column to the spare row or column by means of multiplexer-like logic. Once all fuses have been read and shifted into the repair chain, and the substitutions or repairs have been completed in this manner, the powered-up ASIC can operate normally, as though it had no defective memory locations.
Identifying defective rows or columns and producing the corresponding repair information can be accomplished in a number of ways. One way that has been described is to activate Built-In Self-Test (BIST) logic in the IC to test the memory blocks and activate repair control logic in the IC to burn fuses in accordance with the results of the self-test. External automated test equipment (ATE) can be connected to the IC to provide signals that activate the BIST logic and repair control logic. That is, the signals trigger the IC to test its memory blocks and burn its fuses in the manner described above.
The surface area of an IC die, colloquially referred to as “real estate,” is a limited resource that must be allocated among competing potential uses. Fuses occupy real estate on the IC die that could otherwise be occupied by core logic, such as additional memory. While the time-honored scheme described above provides one fuse for every bit of repair information needed by the entire repair chain, techniques have been described for compressing the repair data such that it consists of fewer bits than the number of bits of repair information needed by the entire repair chain. In one such scheme, the compressed repair information that is stored in the fuses includes binary numbers encoded in a manner that identifies defective rows or columns.